By Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev (auth.), Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso (eds.)
This publication constitutes the refereed complaints of the 3rd overseas Workshop on utilized Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007.
The 27 complete papers and 10 brief papers offered including a late-comer contribution from ARC 2006 have been completely reviewed and chosen from seventy two submissions. The papers are equipped in topical sections on architectures, mapping suggestions and instruments, mathematics, and applications.
Read Online or Download Reconfigurable Computing: Architectures, Tools and Applications: Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. Proceedings PDF
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Additional resources for Reconfigurable Computing: Architectures, Tools and Applications: Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. Proceedings
However, because the ADRES implementation applies static scheduling due to low-power requirements, such dynamic/speculative [6,7] threading is inappropriate. Instead, our threading approach identiﬁes an application’s coarse-grained parallelism based on the static analysis results. If properly reorganized and transformed at programming time, multiple kernels in the same application can be eﬃciently parallelized by the application 28 K. Wu et al. designer. We can statically identify the low-LLP kernels through proﬁling, estimate the optimal choice of ADRES array size for each kernel, and partition a large ADRES array into several small-scaled ADRES sub-arrays that ﬁts each kernel, which is parallelized into threads if possible.
We have also observed that some modulo-scheduled kernels’ IPC do not scale very well when the size of the CGA increases. Some of our most aggressive architectures have the potential to execute 64 instructions per clock cycle, but few applications can utilize this level of parallelism, resulting in a much lower average IPC. This is caused by two reasons: (1) The inherent ILP of the kernels is low and cannot be increased eﬃciently even with loop unrolling, or the code is too complex to be scheduled eﬃciently on so many units due to resource constraints, for example the number of memory ports.
Zalamea, J. Llosa, E. Ayguade, M. Valero Hierarchical clustered register ﬁle organization for VLIW processors, International Parallel and Distributed Processing Symposium, 2003. Proceedings. 22-26 April 2003 Page(s):10 pp. 10. A. Capitanio, N. Dutt, and A. Nicolau. , The 25th Annual International Symposium on Microarchitecture, pages 103–114, Dec. 1992. 11. E. Iwata, K Olukotun Exploiting Coarse-Grain Parallelism in the MPEG-2 Algorithm, Stanford University Computer Systems Lab Technical Report CSL-TR-98771, September 1998.
Reconfigurable Computing: Architectures, Tools and Applications: Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. Proceedings by Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev (auth.), Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso (eds.)