Bias Temperature Instability for Devices and Circuits - download pdf or read online

By Andreas Kerber, Eduard Cartier (auth.), Tibor Grasser (eds.)

ISBN-10: 1461479088

ISBN-13: 9781461479086

ISBN-10: 1461479096

ISBN-13: 9781461479093

This publication offers a single-source connection with one of many tougher reliability matters plaguing sleek semiconductor applied sciences, damaging bias temperature instability. Readers will reap the benefits of state-of-the artwork assurance of analysis in themes corresponding to time established illness spectroscopy, anomalous illness habit, stochastic modeling with extra metastable states, multiphonon concept, compact modeling with RC ladders and implications on equipment reliability and lifetime.

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Extra info for Bias Temperature Instability for Devices and Circuits

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Either spot-Id or spot-CV can be used depending on the device structure. As in the CVS method, minimizing measurement delays is of great interest for the VRS test especially when correlating the results to the CVS test. After the intermittent characterization is completed, the next stress cycle is applied with increased stress bias given by Vstress = Vstart + i ·Vstep, where Vstart is the start voltage, Vstep the step voltage ,and i the cycle index. The step voltage and stress period (tstress ) determine the ramp rate (RR): RR = Vstep .

We measured several different devices of different technology and different substrate types as depicted in Fig. 4. The type and thickness of the substrate have the largest impact on the thermal resistance. For all investigated technologies the data can be reasonably well approximated by a linear relationship, further supporting the previously stated assumptions. 3) can now be compared within the temperature range of the thermo chuck to measurement data, as depicted in Fig. 5. 3) estimates the device temperature with only a few percent relative error.

IRPS, pp. 20–27, 2008. 22. A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, G. E. Maes, U. Schwalke, “Charge trapping in SiO2/HfO2 gate dielectrics: Comparison between charge-pumping and pulsed ID –VG ”, Microelectronic Engineering, Vol. 72, pp. 267–272, 2004. 23. E. N. Kumar, V. D. Maheta, S. Purawat, A. E. Islam, C. Olsen, K. Ahmed, M. A. Alam and S. Mahapatra, “Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique”, Technical Digest.

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