By Sheldon Tan, Lei He
Version order relief (MOR) innovations lessen the complexity of VLSI designs, paving the right way to greater working speeds and smaller function sizes. This e-book offers a scientific creation to, and remedy of, the main MOR tools hired mostly linear circuits, utilizing real-world examples to demonstrate the benefits and drawbacks of every set of rules. Following a evaluate of conventional projection-based concepts, insurance progresses to complicated 'state-of-the-art' MOR tools for VLSI layout, together with HMOR, passive truncated balanced cognizance (TBR) equipment, effective inductance modeling through the VPEC version, and structure-preserving MOR suggestions. the place attainable, numerical tools are approached from the CAD engineer's standpoint, warding off advanced arithmetic and permitting the reader to tackle actual layout difficulties and enhance more desirable instruments. With sensible examples and over a hundred illustrations, this e-book is acceptable for researchers and graduate scholars of electric and desktop engineering, in addition to practitioners operating within the VLSI layout undefined.
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Additional info for Advanced Model Order Reduction Techniques in VLSI Design
5. 6. 7. 8. 3 Solve AWc + Wc AT + BB T = 0 for Wc . Solve AT Wo + Wo A + C T C = 0 for Wo . Compute Cholesky factors, Wc = Lc LTc , Wo = Lo LTo . Compute SVD of Cholesky factors U ΣV T = LTo Lc where Σ is diagonal positive and U ,V have orthonormal columns. Compute the balancing transformation matrices T = Lc V Σ−1/2 , T −1 = Σ−1/2 U T LTo . ˜ = T −1 B, C˜ = Form the balanced realization transformations as A˜ = T −1 AT , B CT . ˜ B, ˜ C˜ conformally. Select reduced model order and partition realization A, ˜ ˜ ˜ Truncate A, B, C to form the reduced realization.
Mr0 = lTr A−1 r br = lT V (W T AV )−1 W T b = g0 T (W T AV )(W T AV )−1 W T r0 = g0 T W T b = lT A−1 b = m0 . In this derivation, we utilize the fact that A−T l belongs to the Krylov subspace Kq (A−T E T , A−T l) and, therefore, A−T l = W g0 and lT = g0 W T A. Then we compare the moment 1 of the reduced system mr1 and that of the original system, m1 . Still we ﬁrst use Krylov subspace colspV = Kq (A−1 E, A−1 b) and we have −1 mr1 = lTr (A−1 r Er )Ar br = lT V (W T AV )−1 W T EV (W T AV )−1 W T b = lT V (W T AV )−1 W T EV r0 = lT V (W T AV )−1 W T A(A−1 E)A−1 b = lT V (W T AV )−1 (W T AV )r1 = lT V r1 = lT (A−1 E)A−1 b = m1 .
If we use multiple terminals, then we end up with block moments. But we only need a few orders of block moments so that the reduced models have larger number of poles than is required. This case is similar to the multiple-input matching in the aforementioned MMM method. The bottom line is that the pole-computation reduction process (its CPU cost) does not depend on the number of terminals of the systems, which is not the case for full-blown Krylov subspace projection-based model order reduction methods to be discussed later.
Advanced Model Order Reduction Techniques in VLSI Design by Sheldon Tan, Lei He